Senior/Staff Digital Design Engineer

OLIX

Job Overview

Location

Austin, United States

Salary

USD 194,000 - 270,000 annual

Employment Type

Full-time

Work Arrangement

On-site

Sector

Information Technology & Software

Experience Level

Senior (5-8 years)

Application Deadline

March 9, 2026

About the Company

OLIX is at the forefront of a technological revolution, building the next paradigm in AI hardware with their innovative Optical Tensor Processing Unit (OTPU). Recognizing the critical infrastructure gap created by the rapid growth of AI, OLIX is developing solutions that offer unprecedented performance and energy efficiency, far surpassing current chip limitations. The company aims to be the most important entity of the next decade by creating a faster, more efficient computing future.

Their mission is to address the limitations of existing hardware blueprints and usher in a new era of computing. OLIX fosters a culture of innovation, collaboration, and ownership, offering employees the chance to be part of a transformative journey and own a piece of the company's success through meaningful stock options.

Job Description

OLIX is seeking highly skilled Senior/Staff Digital Design Engineers to join our innovative team. You will take end-to-end ownership of high-speed, real-time data-processing silicon for our next-generation Optical Tensor Processing Units (OTPU). This role spans from early algorithm modeling to verified RTL and silicon bring-up, operating at the critical intersection of digital, optical, and mixed-signal domains.

You will architect, design, and implement high-throughput digital pipelines in advanced CMOS nodes, and leverage FPGA prototyping for rapid iteration and validation. Your responsibilities will include owning RTL development, performing power, performance, and area (PPA) analysis, and collaborating with cross-functional teams to optimize interfaces and firmware. This is a key role for developing breakthrough AI hardware.

We are looking for individuals with a strong background in electrical engineering and semiconductor physics, coupled with a passion for creating reliable, high-performance digital circuits. If you are ready to drive innovation in AI hardware, we encourage you to apply.

To apply for this role, click the Apply button on this page and follow the instructions.

Required Skills

Digital designASIC designSoC designHigh-speed data processingRTL developmentSystemVerilogVerilogVHDLFPGA prototypingMATLAB/SimulinkPython/NumPyDigital signal processingComputer architectureSemiconductor device physicsSynthesisStatic Timing Analysis (STA)Power analysis (UPF/CPF)Clock Domain Crossing (CDC)Reset Domain Crossing (RDC)LintingGate-level simulationHigh-speed IP integration (SerDes, HBM/DDR, PCIe, 100 GbE)Algorithm modelingFixed-point analysisTest-vector generationCross-functional collaboration

Key Responsibilities

Architect, design and implement high-throughput digital pipelines (multi-GSPS input rate, continuous streaming data paths, deep pipelining and hand-shaking) in advanced CMOS nodes.
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring-up real-time demos, exercise high-speed transceivers, and feed learnings back into the ASIC.
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate-level sign-off.
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static-timing closure, formal and constrained-random verification.
Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth-per-watt targets.
Collaborate with optical-hardware, mixed-signal and software teams to optimise data-converter interfaces, clock-domain crossings and firmware abstractions.
Mentor junior engineers, lead design reviews and champion best-practice design methodologies.

Qualifications

7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream.
Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar).
Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation.
Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab.
Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation.
Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics.
Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment.
Nice to have: Tape-out experience at 22 nm or below.
Nice to have: Knowledge of coherent optical links or photonic-electronic co-design.
Nice to have: Familiarity with AI/ML workloads, systolic arrays or tensor-processing architectures.
Nice to have: Contributions to open-source RTL, verification frameworks or FPGA boards.
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.