Senior/Staff Digital Design Engineer

OLIX

Job Overview

Location

Bristol, United Kingdom

Salary

GBP 125,000 - 180,000 yearly

Employment Type

Full-time

Work Arrangement

On-site

Sector

Information Technology & Software

Experience Level

Senior (5-8 years)

Application Deadline

March 9, 2026

About the Company

OLIX is at the forefront of a technological revolution, addressing the critical infrastructure gap in the rapidly expanding AI landscape. Recognizing that current hardware blueprints are reaching their limits, OLIX is developing a transformative new paradigm: the Optical Tensor Processing Unit (OTPU). This innovative technology promises unprecedented performance and energy efficiency, positioning OLIX to become a leader in the next century's biggest economic opportunity.

The company fosters a dynamic and collaborative environment where digital, optical, and mixed-signal domains converge. OLIX is committed to attracting top global talent and provides comprehensive support, including visa sponsorship and relocation assistance, to build the most important company of the next decade.

Job Description

OLIX is at the vanguard of AI infrastructure, developing the revolutionary Optical Tensor Processing Unit (OTPU) to meet the escalating demands of artificial intelligence. We are seeking highly skilled Senior/Staff Digital Design Engineers to take complete ownership of high-speed, real-time data-processing silicon development. This role spans from initial algorithm modeling through to verified RTL and silicon bring-up, within a dynamic, multidisciplinary team focused on next-generation OTPUs.

You will architect and implement high-throughput digital pipelines, prototype and iterate rapidly on FPGAs, and perform comprehensive RTL development and verification. A key aspect of this role involves analyzing power, performance, and area (PPA) to achieve aggressive bandwidth-per-watt targets. Collaboration with optical-hardware, mixed-signal, and software teams is crucial for optimizing interfaces and firmware. Mentoring junior engineers and championing best practices will also be integral to your responsibilities.

To apply for this role, click the Apply button on this page and follow the instructions.

Required Skills

CMOS digital designRTL developmentSystemVerilogVerilogVHDLFPGA prototypingMATLAB/SimulinkPython/NumPyDigital Signal ProcessingComputer ArchitectureSemiconductor PhysicsEDA flowsSynthesisStatic Timing Analysis (STA)Power Intent (UPF/CPF)LintGate-level simulationHigh-speed IP integrationSerDesHBM/DDRPCIe100 GbE

Key Responsibilities

Architect, design, and implement high-throughput digital pipelines (multi-GSPS input rate, continuous streaming data paths, deep pipelining and hand-shaking) in advanced CMOS nodes.
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring-up real-time demos, exercise high-speed transceivers, and feed learnings back into the ASIC.
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate-level sign-off.
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static-timing closure, formal and constrained-random verification.
Analyze power, performance, and area (PPA); implement innovative techniques to achieve aggressive bandwidth-per-watt targets.
Collaborate with optical-hardware, mixed-signal and software teams to optimise data-converter interfaces, clock-domain crossings and firmware abstractions.
Mentor junior engineers, lead design reviews and champion best-practice design methodologies.

Qualifications

7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream.
Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar).
Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation.
Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab.
Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation.
Solid grounding in digital signal-processing concepts, computer-architecture fundamentals and semiconductor device physics.
Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment.

Benefits & Perks

Competitive Salary: £125,000 - £180,000
Equity & Ownership: Meaningful stock options
Proximity Bonus: £24k annual Living-Local Bonus
Premium Healthcare: Comprehensive BUPA medical and dental cover
Time Off: 25 days of annual leave, plus all UK bank holidays
Elite Hardware: M4 Macs as standard, M4 Pro upgrades for engineering
Optimal Environment: High-spec noise-cancelling headphones and ergonomic workstation
Rapid Prototyping: Access to high-performance 3D printing lab
Chef-prepared meals (if working late)
Caffeine allowance at a local coffee shop
Full UK and international visa sponsorship
Seamless relocation support